Semiconductor device and method of fabricating the same

ABSTRACT

A semiconductor device includes a substrate, a gate electrode on the substrate, a gate spacer on a sidewall of the gate electrode, an active pattern penetrating the gate electrode and the gate spacer, and an epitaxial pattern contacting the active pattern and the gate spacer. The gate electrode extends in a first direction. The gate spacer includes a semiconductor material layer. The active pattern extends in a second direction crossing the first direction.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims priority under 35 U.S.C. § 119 to Korean PatentApplication No. 10-2017-0180511, filed on Dec. 27, 2017, in the KoreanIntellectual Property Office, the disclosure of which is herebyincorporated by reference in its entirety.

FIELD

Example embodiments of the present disclosure relate to a semiconductordevice and a method of fabricating the same, and more specifically, to asemiconductor device having a gate all around structure and a method offabricating the same.

BACKGROUND

To increase the integration of an integrated circuit device, amulti-gate transistor including a silicon body of a fin- ornanowire-shape on a substrate and a gate on the silicon body has beenproposed.

Since a multi-gate transistor can utilize a three-dimensional channel,it can be scaled. Further, current control capability of the multi-gatetransistor can be improved without increasing a gate length thereof.Short channel effects (SCE), in which the electrical potential of thechannel region is affected by the drain voltage, can be effectivelyreduced and/or suppressed in the multi-gate transistor.

SUMMARY

According to example embodiments of the inventive concepts, asemiconductor device may include a substrate, a gate electrode on thesubstrate, a gate spacer on a sidewall of the gate electrode, an activepattern penetrating the gate electrode and the gate spacer, and anepitaxial pattern contacting the active pattern and the gate spacer. Thegate electrode may extend in a first direction. The gate spacer mayinclude a semiconductor material layer. The active pattern may extend ina second direction crossing the first direction.

According to example embodiments of the inventive concepts, asemiconductor device may include a substrate, a first active pattern onthe substrate, a gate electrode surrounding the first active pattern, aninner spacer on a sidewall of the gate electrode, and an epitaxialpattern contacting the first active pattern and the inner spacer. Theinner spacer may be between the first active pattern and the substrateand include a semiconductor material.

According to example embodiments of the inventive concepts, asemiconductor device may include a substrate including a first regionand a second region, a first gate electrode on the first region, a firstgate spacer on a sidewall of the first gate electrode, a first activepattern penetrating the first gate electrode, a first epitaxial patternon a sidewall of the first gate spacer, a second gate electrode on thesecond region, a second active pattern penetrating the second gateelectrode, and a second epitaxial pattern on a side of the second gateelectrode. The first gate electrode may extend in a first direction. Thefirst gate spacer may include a first semiconductor material. The firstactive pattern may extend in a second direction crossing the firstdirection. The second gate electrode extend in a third direction. Thesecond active pattern may extend in a fourth direction crossing thethird direction.

According to example embodiments of the inventive concepts, a method ofmanufacturing a semiconductor device may include forming a fin structureincluding at least one sacrificial pattern and at least one activepattern which are alternately stacked on a substrate, selectively recessa sidewall of the at least one sacrificial pattern, forming an innerspacer layer along a sidewall of the at least one active pattern and therecessed sidewall of the at least one sacrificial pattern, forming aninner spacer on the recessed sidewall of the at least one sacrificialpattern by removing a portion of the inner spacer layer on the sidewallof the at least one active pattern, and forming an epitaxial patterncontacting the inner spacer and the at least one active pattern.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a perspective view of a semiconductor device according toexample embodiments.

FIG. 2 is a cross-sectional view taken along line A-A′ of FIG. 1.

FIGS. 3A and 3B are enlarged views of portion R1 of FIG. 2.

FIG. 4 is a cross-sectional view taken along line B-B′ of FIG. 1.

FIG. 5 is a cross-sectional view of a semiconductor device according toexample embodiments.

FIG. 6 is a cross-sectional view of a semiconductor device according toexample embodiments.

FIG. 7 is an enlarged view of portion R2 of FIG. 6.

FIG. 8 is a cross-sectional view of a semiconductor device according toexample embodiments.

FIG. 9 is a perspective view of a semiconductor device according toexample embodiments.

FIG. 10 is a cross-sectional view taken along lines C-C′ and D-D′ ofFIG. 9.

FIG. 11 is a perspective view of a semiconductor device according toexample embodiments.

FIG. 12 is a cross-sectional view taken along lines E-E′ and F-F′ ofFIG. 11.

FIG. 13 is a perspective view of a semiconductor device according toexample embodiments.

FIGS. 14 and 15 are cross-sectional views taken along lines G-G′ andH-H′ of FIG. 13.

FIGS. 16 to 29 are views illustrating stages in a method ofmanufacturing an image sensor according to example embodiments.

DETAILED DESCRIPTION

Various example embodiments will now be described more fully hereinafterwith reference to the accompanying drawings. Like reference numerals mayrefer to like elements throughout this application.

Hereinafter, a semiconductor device according to example embodimentswill described with reference to FIGS. 1 to 15. For convenience ofexplanation, a device isolation layer such as a shallow trench isolation(STI) is omitted in the drawings.

FIG. 1 is a perspective view of a semiconductor device according toexample embodiments. FIG. 2 is a cross-sectional view taken along lineA-A′ of FIG. 1. FIGS. 3A and 3B are enlarged views of portion R1 of FIG.2. FIG. 4 is cross-sectional view taken along line B-B′ of FIG. 1. Aninterlayer insulation layer 160 is not illustrated in FIG. 1, forbrevity.

Referring to FIGS. 1 to 4, a semiconductor device includes a substrate100, a field insulation layer 105, a first active pattern 110, a secondactive pattern 120, a first gate structure 150, first gate spacers 130,first epitaxial patterns 140, and the interlayer insulation layer 160.As used herein, the terms first, second, third, etc. are used merely todifferentiate one direction, region, portion, or element from another.

The substrate 100 may include a bulk silicon substrate or a silicon oninsulator (SOI) substrate. In some embodiments, the substrate 100 mayinclude, e.g., at least one of silicon germanium, silicon germanium oninsulator (SGOI), indium antimonide, lead-tellurium compound, indiumarsenic, indium phosphide, gallium arsenic, or gallium antimonide. Thesubstrate 100 may include an epitaxial layer on a base substrate.Hereinafter, it will be described that the substrate 100 includessilicon, for convenience of description.

The substrate 100 includes a first fin protrusion 100P. The first finprotrusion 100P may protrude from an upper surface of the substrate 100and extend lengthwise in a first direction X1. Spatially relative terms,such as “beneath,” “below,” “lower,” “above,” “upper” “higher,” and thelike, are intended to encompass different orientations of the device inuse or operation in addition to the orientation depicted in the figures.The first fin protrusion 100P may be formed by etching a portion of thesubstrate 100, or may be an epitaxial layer grown from the substrate100.

The first fin protrusion 100P may include silicon or germanium. In someembodiments, the first fin protrusion 100P may include a compoundsemiconductor, e.g., a group IV-IV compound semiconductor or a groupIII-V compound semiconductor.

The group IV-IV compound semiconductor may include a binary compound ora ternary compound, each of which includes at least two of carbon (C),silicon (Si), germanium (Ge), or tin (Sn), or a compound which a groupIV element is doped therein.

The group III-V compound semiconductor may include a binary compound, aternary compound, or a quaternary compound, each of which is formed bycombination of a group III element, e.g., at least one of aluminum (Al),gallium (Ga), or indium (In), and a group V element, e.g., at least oneof phosphorus (P), arsenic (As), or antimony (Sb).

The field insulation layer 105 may be formed on the substrate 100. Thefield insulation layer 105 may surround at least a portion of a sidewallof the first fin protrusion 100P. As used herein, the term “surround”does not require completely or entirely surrounding. The first finprotrusion 100P may be defined by the field insulation layer 105.

Referring to FIG. 4, sidewalls of the first active pattern 110 and thesecond active pattern 120 may be partially or entirely surrounded by thefield insulation layer 105. However, the inventive concepts are notlimited thereto.

The field insulation layer 105 may include, e.g., a silicon oxide layer,a silicon nitride layer, a silicon oxynitride layer, or combinationsthereof.

The first active pattern 110 may be formed on the substrate 100. Thefirst active pattern 110 may be spaced apart from the substrate 100. Thefirst active pattern 110 may extend in the first direction X1.

The first active pattern 110 may be formed on the first fin protrusion100P and be spaced apart from the first fin protrusion 100P. The firstactive pattern 110 may vertically overlap the first fin protrusion 100P.For example, the first active pattern 110 may overlap the first finprotrusion 100P in a third direction Z1. Thus, the first active pattern110 may not be formed on the field insulation layer 105, but may beformed on the first fin protrusion 100P.

The second active pattern 120 may be formed on the first active pattern110. The second active pattern 120 may be spaced apart from the firstactive pattern 110. The second active pattern 120 may extend in thefirst direction X1. The second active pattern 120 may vertically overlapthe first active pattern 110. For example, the second active pattern 120may overlap the first active pattern 110 in the third direction Z1.

The first active pattern 110 and the second active pattern 120 mayinclude silicon or germanium. In some embodiments, the first activepattern 110 and the second active pattern 120 may include a compoundsemiconductor, e.g., a group IV-IV compound semiconductor or a groupIII-V compound semiconductor.

The first active pattern 110 and the second active pattern 120 mayinclude the same material as or a different material from the first finprotrusion 100P.

Each of the first active pattern 110 and the second active pattern 120may be used as a channel region of a transistor.

Even though semiconductor devices including two active patterns areillustrated in the drawings, the inventive concepts are not limitedthereto. For example, semiconductor devices may include one or more thanthree active patterns.

The first gate structure 150 includes a first gate insulation layer 152and a first gate electrode 154.

The first gate electrode 154 may be formed on the substrate 100. Thefirst gate electrode 154 may intersect the first active pattern 110 andthe second active pattern 120. For example, the first gate electrode 154may extend lengthwise in a second direction Y1.

The first gate electrode 154 may surround the first active pattern 110and the second active pattern 120. For example, the first active pattern110 and the second active pattern 120 may penetrate or extend throughthe first gate electrode 154 in the first direction X1. The first gateelectrode 154 may entirely surround or otherwise extend along aperimeter of the first active pattern 110 and a perimeter of the secondactive pattern 120. The first gate electrode 154 may be disposed betweenthe first active pattern 110 and the substrate 100.

The first gate electrode 154 may include a conductive material. Thefirst gate electrode 154 may be formed of a single layer or multiplelayers. For example, the first gate electrode 154 may include a workfunction control conductive layer and a filling conductive layer whichfills a space formed by the work function control conductive layer.

The first gate electrode 154 may include, e.g., TiN, WN, TaN, Ru, TiC,TaC, Ti, Ag, Al, TiAl, TiAlN, TiAlC, TaCN, TaSiN, Mn, Zr, W, Al, orcombinations thereof. In some embodiments, the first gate electrode 154may include silicon or silicon germanium. The first gate electrode 154may be formed by a gate replacement process, but the inventive conceptsare not limited thereto.

The first gate spacers 130 may be formed on opposite sidewalls of thefirst gate electrode 154 and extend in the second direction Y1. Thefirst gate spacers 130 may define a first trench TR1 crossing the firstactive pattern 110 and the second active pattern 120.

The first gate spacers 130 may be formed on opposite end portions of thefirst and second active patterns 110 and 120. For example, the firstgate spacers 130 may contact the opposite end portions of the first andsecond active patterns 110 and 120. The term “contact” may mean thatthere are no intervening elements (e.g., layers or substrates) presentbetween the contacting elements. In contrast, when an element isreferred to as being “on” or “adjacent” another element, it may contactthe other element, or intervening elements may also be present. In someembodiments, the first active pattern 110 and/or the second activepattern 120 may penetrate or extend through the first gate spacers 130.

Each of the first gate spacers 130 includes a first outer spacer 132 anda first inner spacer 134.

The first inner spacer 134 may be formed on a sidewall of a portion ofthe first gate electrode 154 that surrounds the first active pattern 110and the second active pattern 120. The first outer spacer 132 may beformed on the first inner spacer 134. The first outer spacer 132 may bedisposed on the second active pattern 120. For example, referring toFIGS. 2 and 3, the first inner spacer 134 may be disposed between thefirst fin protrusion 100P and the first active pattern 110. The firstinner spacer 134 may also be disposed between the first active pattern110 and the second active pattern 120.

In some embodiments, the first inner spacer 134 and the first outerspacer 132 may be disposed on the second active pattern 120, inaccordance with a multi-layered stack structure for forming the firstand second active patterns 110 and 120.

Referring to FIG. 2, a width of the first outer spacer 132 may be equalto a width of the first inner spacer 134. Herein, the width of the firstouter spacer 132 and the width of the first inner spacer 134 refer to afirst width W11 of the first outer spacer 132 and a second width W12 ofthe first inner spacer 134, respectively, in the first direction X1. Insome embodiment, the first width W11 of the first outer spacer 132 maybe less or greater than the second width W12 of the first inner spacer134.

The first gate spacers 130 may include a material similar to the firstactive pattern 110 and the second active pattern 120. For example, thefirst gate spacers 130 may include a semiconductor material layer. Thesemiconductor material layer may include a semiconductor material. Thesemiconductor material may not include an insulating material, such asoxide or nitride. That is, the first gate spacers 130 may be free ofoxides, nitrides, and/or other insulating materials.

In some embodiments, the first inner spacer 134 of each of the firstgate spacers 130 may include a semiconductor material layer.

For example, when the first active pattern 110 and the second activepattern 120 include silicon, the first inner spacer 134 may includesilicon (Si) or silicon germanium (SiGe). In this case, a siliconconcentration in the first inner spacer 134 may be greater than that ineach of the first active pattern 110 and the second active pattern 120,for example. In some embodiments, when the first active pattern 110 andthe second active pattern 120 include germanium (Ge) or silicongermanium (SiGe), the first inner spacer 134 may include germanium (Ge)or silicon germanium (SiGe). In this case, a germanium concentration inthe first inner spacer 134 may be greater than that in each of the firstactive pattern 110 and the second active pattern 120, for example.

The first outer spacer 132 may be the same material as or a differentmaterial from the first inner spacer 134.

In some embodiments, the first outer spacer 132 may include aninsulating material layer. For example, the first outer spacer 132 mayinclude silicon nitride, silicon oxynitride, silicon oxide, silconoxycarbonitride, or combinations thereof.

The first gate insulation layer 152 may be disposed between the firstactive pattern 110 and the first gate electrode 154 and between thesecond active pattern 120 and the first gate electrode 154. Thus, thefirst gate insulation layer 152 may be formed along surfaces of thefirst active pattern 110 and the second active pattern 120. The firstgate insulation layer 152 may surround the first active pattern 110 andthe second active pattern 120. Additionally, the first gate insulationlayer 152 may be formed on an upper surface of the field insulationlayer 105 and on an upper surface of the first fin protrusion 100P.

The first gate insulation layer 152 may extend along inner sidewalls ofthe first gate spacers 130. For example, the first gate insulation layer152 may extend along sidewalls and a lower surface of the first trenchTR1.

The first gate insulation layer 152 may include a high-k dielectricmaterial having a dielectric constant greater than that of siliconoxide, silicon nitride, or silicon oxynitride. For example, the firstgate insulation layer 152 may include, e.g., hafnium oxide, hafniumsilicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanumaluminum oxide, zirconium oxide, zirconium silicon oxide, tantalumoxide, titanium oxide, barium strontium titanium oxide, barium titaniumoxide, strontium titanium oxide, yttrium oxide, aluminum oxide, leadscandium tantalum oxide, or lead zinc niobate, or combinations thereof,but is not limited thereto.

Even though not shown in the drawings, an interfacial layer may beformed between the first gate insulation layer 152 and the first activepattern 110 and between the first gate insulation layer 152 and thefirst fin protrusion 100P. According to a method of forming theinterfacial layer, the interfacial layer may be formed along a profileor periphery of the first gate insulation layer 152. However, theinventive concepts are not limited thereto.

The first epitaxial patterns 140 may be formed on opposite sides of thefirst gate electrode 154. The first epitaxial patterns 140 may contactthe first active pattern 110, the second active pattern 120, and thefirst gate spacers 130. For example, the first epitaxial patterns 140may be formed on sidewalls of the first active pattern 110, sidewalls ofthe second active pattern 120, and outer sidewalls of the respectivefirst gate spacers 130.

Each of the first epitaxial patterns 140 may include an epitaxial layerformed on the first fin protrusion 100P. The first epitaxial patterns140 may be elevated source/drain regions having upper surfacesprotruding above the upper surface of the substrate 100. However, theinventive concepts are not limited thereto. The first epitaxial patterns140 may be impurity regions formed in the substrate 100.

In some embodiments, each of the first epitaxial patterns 140 mayinclude multiple layers. For example, each of the first epitaxialpatterns 140 includes a first epitaxial layer 142 and a second epitaxiallayer 144 that are sequentially formed on the substrate 100.

The first epitaxial layer 142 may be formed on the first fin protrusion100P, the first active pattern 110, the second active pattern 120, andthe first inner spacer 134. The first epitaxial layer 142 may be formedfrom the first fin protrusion 100P, the first active pattern 110, thesecond active pattern 120, and the first inner spacer 134, by anepitaxial growth process. The first epitaxial layer 142 may extend alongthe upper surface of the first fin protrusion 100P, the sidewall of thefirst active pattern 110, the sidewall of the second active pattern 120,and an outer sidewall of the first inner spacer 134.

The first epitaxial layer 142 may act as a seed to grow each of thefirst epitaxial patterns 140. However, in some embodiments, the firstepitaxial layer 142 may be omitted.

The second epitaxial layer 144 may be formed on the first epitaxiallayer 142. The second epitaxial layer 144 may be formed to fill a trenchformed on the substrate 100.

The second epitaxial layer 144 may have a cross section of diamondshape, pentagonal shape, or hexagonal shape. However, the inventiveconcepts are not limited thereto. The second epitaxial layer 144 mayhave cross sections of various shapes.

In some embodiments, when the semiconductor device is a PMOS transistor,the first epitaxial patterns 140 may include a p-type impurity or animpurity for preventing diffusion of the p-type impurity. For example,the first epitaxial patterns 140 may include B, C, In, Ga, Al, orcombinations thereof.

In some embodiments, when the semiconductor device is a PMOS transistor,the first epitaxial patterns 140 may include a compressive stressmaterial, that is, a material that is configured to induce a compressivestress or strain. For example, when each of the first active pattern 110and the second active pattern 120 is a silicon pattern, the firstepitaxial patterns 140 may include a material having a lattice constantgreater than that of silicon. For example, the first epitaxial patterns140 may include silicon germanium (SiGe). The compressive stressmaterial may apply a compressive stress to the first and second activepatterns 110 and 120, such that a carrier mobility in the channel region(e.g., the first and second active patterns 110 and 120) of thetransistor may be increased.

In some embodiments, when the semiconductor device is an NMOStransistor, the first epitaxial patterns 140 may include an n-typeimpurity or an impurity for preventing diffusion of the n-type impurity.For example, the first epitaxial patterns 140 may include P, Sb, As, orcombinations thereof.

In some embodiments, when the semiconductor device is an NMOStransistor, the first epitaxial patterns 140 may include a tensilestress material, that is, a material that is configured to induce atensile stress or strain. For example, when each of the first activepattern 110 and the second active pattern 120 is a silicon pattern, thefirst epitaxial patterns 140 may include a material having a latticeconstant smaller than that of silicon. For example, the first epitaxialpatterns 140 may include silicon carbon (SiC). The tensile stressmaterial may apply a tensile stress to the first and second activepatterns 110 and 120, such that a carrier mobility in the channel region(e.g., the first and second active patterns 110 and 120) of thetransistor may be increased. In some embodiments, the first epitaxialpatterns 140 may not include the tensile stress material.

In some embodiments, the first epitaxial layer 142 and the secondepitaxial layer 144 may include a first semiconductor material atvarious concentrations. For example, when the semiconductor device is aPMOS transistor, the first epitaxial layer 142 may include the firstsemiconductor material, that is a compressive stress material, at afirst concentration. When the first and second active patterns 110 and120 include silicon (Si), the first semiconductor material may be, e.g.,germanium (Ge).

At this time, the second epitaxial layer 144 may include the firstsemiconductor material at a second concentration different from thefirst concentration. For example, a germanium concentration in thesecond epitaxial layer 144 may be greater than that in the firstepitaxial layer 142. The first concentration may range from 10% to 30%,and the second concentration may range from 40% to 65%. As theconcentration of the first semiconductor material increases, thecompressive stress imparted on the channel region (e.g., the first andsecond active patterns 110 and 120) of the transistor may be increased.Thus, the second epitaxial layer 144 including the first semiconductormaterial at the second concentration greater than the firstconcentration may serve to increase the carrier mobility.

In some embodiments, the first concentration may be equal to the secondconcentration.

In some embodiments, a portion of each of the first epitaxial patterns140 that is adjacent to the first active pattern 110, the second activepattern 120, and the first gate spacers 130 may include a firstsemiconductor material at a high concentration. For example, a germaniumconcentration of the first epitaxial layer 142 may be more than 30%.

The interlayer insulation layer 160 may be formed on the substrate 100.The interlayer insulation layer 160 may surround the outer sidewalls ofthe first gate spacers 130 defining the first trench TR1.

The interlayer insulation layer 160 may include, e.g., silicon oxide,silicon nitride, silicon oxynitride, and/or a low-k dielectric material.The term “and/or” includes any and all combinations of one or more ofthe associated listed items. The low-k dielectric material may include,e.g., Flowable Oxide (FOX), Torene SilaZene (TOSZ), Undoped Silica Glass(USG), Borosilica Glass (BSG), PhosphoSilica Glass (PSG),BoroPhosphoSilica Glass (BPSG), Plasma Enhanced Tetra Ethyl OrthoSilicate (PETEOS), Fluoride Silicate Glass (FSG), Carbon Doped siliconOxide (CDO), Xerogel, Aerogel, Amorphous Fluorinated Carbon, OrganoSilicate Glass (OSG), Parylene, bis-benzocyclobutenes (BCB), SiLK,polyimide, porous polymeric material, or combinations thereof, but isnot limited thereto.

In some embodiments, the first gate spacers 130 may include an impurity.For example, the first inner spacer 134 of each of the first gatespacers 130 may include a p-type impurity or an n-type impurity. Thatis, the first inner spacer 134 may be p-type or n-type.

The first gate spacers 130 may include an impurity of the same type asor a different type from (e.g., the same conductivity type as or adifferent conductivity type than) the first epitaxial patterns 140.

For example, the first epitaxial patterns 140 may include a firstimpurity, and the first gate spacers 130 may include a second impurityof the same conductive type as the first impurity. For example, as shownin FIG. 3A, each of the first epitaxial patterns 140 and the first innerspacer 134 may include a p-type impurity.

In this case, the first inner spacer 134 may improve the performance ofthe semiconductor device. For example, when the first epitaxial patterns140 include the first impurity at a low concentration, the first innerspacer 134 may include the second impurity at a higher concentrationthan that of the first impurity, such that the performance of thesemiconductor device may be improved. In some embodiments, theconcentration of the second impurity may be substantially equal to orlower than that of the first impurity.

In some embodiments, the first epitaxial patterns 140 may include afirst impurity, and the first gate spacers 130 may include a secondimpurity of a different type from the first impurity. For example, asshown in FIG. 3B, the first epitaxial patterns 140 may include a p-typeimpurity, and the first inner spacer 134 may include an n-type impurity.

In this case, the first inner spacer 134 may effectively suppress ashort channel effect (SCE). For example, when the first epitaxialpatterns 140 include the first impurity at a high concentration, thefirst impurity may be diffused into the channel region (e.g., the firstactive pattern 110 and the second active pattern 120), such that the SCEmay intensify. However, the second impurity having the differentconductive type from the first impurity may be diffused into the firstactive pattern 110 and the second active pattern 120 adjacent thereto,the SCE may be effectively suppressed.

In semiconductor devices according to example embodiments, defects inthe source/drain region may be reduced or prevented from occurring. Forexample, a stacking fault in the source/drain region may be reduced orprevented from occurring.

The source/drain region may be formed from the active pattern and thegate spacer by an epitaxial growth process. However, the source/drainregion may include stacking faults therein due to the difference inlattice constants between the active pattern and the gate spacer. Thismay make it difficult to improve the performance of the semiconductordevice. Thus, the performance of the semiconductor device may be reducedor lowered.

However, in semiconductor devices according to example embodiments, thefirst gate spacers 130 including the semiconductor material layersimilar to the first and second active patterns 110 and 120 may be used,such that stacking faults in the source/drain regions (e.g., the firstepitaxial patterns 140) may be reduced or prevented from being formed.Additionally, the source/drain regions (e.g., the first epitaxialpatterns 140) may be prevented from being damaged or the likelihood ofdamage may be reduced.

To manufacture semiconductor devices having a gate all around (GAA)structure, active layers (see, e.g., 2002 of FIG. 16) and sacrificiallayers (see, e.g., 2001 of FIG. 16) having an etch selectivity withrespect to one another may be used. For example, the sacrificial layers(see, e.g., 2001 of FIG. 16) including germanium (Ge) may have etchselectivity with respect to the active layers (see, e.g., 2002 of FIG.16) including silicon (Si). When the semiconductor device is a PMOStransistor, the first epitaxial patterns 140 may also include germanium(Ge). Thus, due to a low etch selectivity in a removal process of thesacrificial layers (see, e.g., 2001 of FIG. 16), the first epitaxialpatterns 140 may be damaged. Accordingly, the performance andreliability of the semiconductor device may be reduced or lowered.

However, in semiconductor devices according to example embodiments, thefirst gate spacers 130 including the semiconductor material layersimilar to the first and second active patterns 110 and 120 (that arethe channel region) may be used to reduce or prevent the damage to thesource/drain regions (e.g., the first epitaxial patterns 140). Forexample, the first gate spacers 130 may include the semiconductormaterial layer similar to the first and second active patterns 110 and120 such that the first epitaxial patterns 140 are protected from beingdamaged in the removal process of the sacrificial layers (see, e.g.,2001 of FIG. 16) due to the etch selectivity of the first gate spacers130.

FIG. 5 is a cross-sectional view illustrating a semiconductor deviceaccording to example embodiments. In FIG. 5, the same numerals are usedto denote the same elements as shown in FIGS. 1 to 4.

Referring to FIG. 5, in a semiconductor device according to exampleembodiments, the first inner spacer 134 may be formed of multiplesections. For example, the first inner spacer 134 includes a first subspacer 134 a and a second sub spacer 134 b.

The first sub spacer 134 a may be formed along a profile of a surface ofthe first gate insulation layer 152. The second sub spacer 134 b may beformed on a sidewall of the first sub spacer 134 a.

In some embodiments, the first sub spacer 134 a and the second subspacer 134 b may include a semiconductor material at differentconcentrations.

For example, when the first active pattern 110 and the second activepattern 120 include silicon (Si), the first sub spacer 134 a and thesecond sub spacer 134 b may include silicon (Si) or silicon germanium(SiGe). In this case, a silicon concentration in the first sub spacer134 a may be higher than that in the second sub spacer 134 b. Thus, inthe removal process of the sacrificial layers (see, e.g., 2001 of FIG.16) including germanium (Ge), the first epitaxial patterns 140 may beprotected from being damaged due to the etch selectivity of the firstsub spacer 134 a.

In some embodiments, when the first active pattern 110 and the secondactive pattern 120 include silicon germanium (SiGe) or germanium (Ge),the first sub spacer 134 a and the second sub spacer 134 b may includesilicon germanium (SiGe) or germanium (Ge). In this case, a germaniumconcentration in the first sub spacer 134 a may be higher than that inthe second sub spacer 134 b. Thus, in the removal process of thesacrificial layers (see, e.g., 2001 of FIG. 16) including silicon (Si),the first epitaxial patterns 140 may be protected from being damaged dueto the etch selectivity of the first sub spacer 134 a.

In some embodiments, the first sub spacer 134 a may include aninsulating material, and the second sub spacer 134 b may include asemiconductor material layer similar to the first active pattern 110 andthe second active pattern 120.

For example, the first sub spacer 134 a may include a low-k dielectricmaterial, silicon nitride, silicon oxynitride, silicon oxide, siliconoxycarbonitride, or combinations thereof. The low-k dielectric materialof the first sub spacer 134 a may be a material having a dielectricconstant smaller than that of silicon oxide. The first sub spacer 134 amay serve to reduce a parasitic capacitance between the first gateelectrode 154 and the first epitaxial patterns 140.

For example, when the first active pattern 110 and the second activepattern 120 include silicon (Si), the second sub spacer 134 b mayinclude silicon (Si) or silicon germanium (SiGe). For example, when thefirst active pattern 110 and the second active pattern 120 includesilicon germanium (SiGe) or germanium (Ge), the second sub spacer 134 bmay include silicon germanium (SiGe) or germanium (Ge). The second subspacer 134 b may serve to reduce or prevent stacking faults in the firstepitaxial patterns 140 from being formed.

FIG. 6 is a cross-sectional view of a semiconductor device according toexample embodiments. FIG. 7 is an enlarged view of portion R2 of FIG. 6.In FIGS. 6 and 7, the same numerals are used to denote the same elementsas shown in FIGS. 1 to 4.

Referring to FIGS. 6 and 7, in a semiconductor device according toexample embodiments, at least one sidewall of the first inner spacer 134may have a curved surface. For example, a first sidewall 134S1 of thefirst inner spacer 134 adjacent to the first gate electrode 154 may havea convex curved shape toward the first gate electrode 154.

The first gate insulation layer 152 may extend along a profile of thefirst sidewall 134S1 of the first inner spacer 134. Thus, a surface of aportion of the first gate insulation layer 152 adjacent to the firstinner spacer 134 may be concavely curved toward the first inner spacer134. Likewise, a sidewall of the first gate electrode 154 adjacent tothe first inner spacer 134 may be concavely curved. That is, the firstsidewall 134S1 of the first inner spacer 134 may conformally extendalong the sidewall of the gate electrode structure 152, 154.

A second sidewall 134S2 of the first inner spacer 134 adjacent to eachof the first epitaxial patterns 140 may be flat or planar, but is notlimited thereto. In some embodiments, the second sidewall 134S2 of thefirst inner spacer 134 may have a profile similar to the first sidewall134S1 thereof. For example, the second sidewall 134S2 of the first innerspacer 134 may have a concave curved shape.

In some embodiments, a width of the first inner spacer 134 in the firstdirection X1 may be varied. For example, a third width W21 of a portionof the first inner spacer 134 adjacent to the first active pattern 110or the second active pattern 120 may be smaller than a fourth width W22of a middle portion of the first inner spacer 134.

In some embodiments, the sidewall of the first inner spacer 134 adjacentto the first active pattern 110 or the second active pattern 120 may beat an obtuse angle with respect to the first active pattern 110 or thesecond active pattern 120. For example, the first sidewall 134S1 of thefirst inner spacer 134 may be at an obtuse angle with respect to a lowersurface of the second active pattern 120.

The shape of the first inner spacer 134 may be formed by a process offabricating semiconductor devices to be described later with referenceto FIGS. 24 to 26.

FIG. 8 is a cross-sectional view illustrating a semiconductor deviceaccording to example embodiments. In FIG. 8, the same numerals are usedto denote the same elements as shown in FIGS. 1 to 4, 6, and 7.

Referring to FIG. 8, in a semiconductor device, the first inner spacer134 may extend (e.g., continuously) along the upper surface of the firstfin protrusion 100P, the sidewall of the first active pattern 110, andthe sidewall of the second active pattern 120.

For example, the first inner spacer 134 may extend along a profile ofthe first fin protrusion 100P, a profile of the first gate insulationlayer 152, a profile of the first active pattern 110, and a profile ofthe second active pattern 120. Thus, the first inner spacer 134 may beinterposed between the first active pattern 110 and each of the firstepitaxial patterns 140 and between the second active pattern 120 andeach of the first epitaxial patterns 140.

In some embodiments, the first epitaxial layer 142 of each of the firstepitaxial patterns 140 may extend along a profile of the first innerspacer 134. In other embodiments, the first epitaxial layer 142 may beomitted.

In some embodiments, the first inner spacer 134 may include an impurity.For example, when the semiconductor device is a PMOS transistor, thefirst inner spacer 134 may include a p-type impurity. In this case, ajunction region of the PMOS transistor may be adjusted depending on aconcentration of the p-type impurity in the first inner spacer 134.

FIG. 9 is a perspective view of a semiconductor device according toexample embodiments. FIG. 10 is a cross-sectional view taken along linesC-C′ and D-D′ of FIG. 9. In FIGS. 9 and 10, the same numerals are usedto denote the same elements as shown in FIGS. 1 to 4.

Referring to FIGS. 9 and 10, in a semiconductor device according toexample embodiments, the substrate 100 includes a first region I and asecond region II. The first region I and the second region II may bespaced apart from or be connected to each other. Transistors of the sameconductive type or transistors of different conductive types may beformed on the first region I and the second region II.

The first region I and the second region II may each be, e.g., a logicregion, an SRAM region, or an input/output (IO) region. For example, thefirst region I and the second region II may be regions on whichsemiconductor devices for performing the same function or differentfunctions are disposed.

In some embodiments, the semiconductor device on the first region I isthe same as that described with reference to FIGS. 1 to 4, and thus adetailed description thereof is omitted.

The semiconductor device on the second region II includes a second finprotrusion 200P, a third active pattern 210, a fourth active pattern220, a second gate structure 250, second gate spacers 230, and secondepitaxial patterns 240.

The second fin protrusion 200P may protrude from the upper surface ofthe substrate 100 and extend lengthwise in a fourth direction X2. Thesecond fin protrusion 200P may be formed by etching a portion of thesubstrate 100 or may be an epitaxial layer grown from the substrate 100.

The third active pattern 210 may be formed on the substrate 100. Thethird active pattern 210 may be spaced apart from the substrate 100. Thethird active pattern 210 may extend in the fourth direction X2.

The fourth active pattern 220 may be formed on the third active pattern210 and be spaced apart from the third active pattern 210. The fourthactive pattern 220 may extend in the fourth direction X2.

The third active pattern 210 and the fourth active pattern 220 mayinclude the same material as or a different material from the firstactive pattern 110 and the second active pattern 120.

The second gate structure 250 includes a second gate insulation layer252 and a second gate electrode 254.

The second gate electrode 254 may be formed on the substrate 100. Thesecond gate electrode 254 may intersect the third active pattern 210 andthe fourth active pattern 220. The second gate electrode 254 may extendlengthwise in a fifth direction Y2.

The second gate electrode 254 may surround the third active pattern 210and the fourth active pattern 220. The third active pattern 210 and thefourth active pattern 220 may penetrate or extend through the secondgate electrode 254.

The second gate spacers 230 may be disposed on sidewalls of the secondgate electrode 254. The second gate spacers 230 may define a secondtrench TR2 crossing the third active pattern 210 and the fourth activepattern 220.

The second gate spacers 230 may be disposed on opposite end portions ofthe third active pattern 210 and/or the fourth active pattern 220. Insome embodiments, the third active pattern 210 and the fourth activepattern 220 may penetrate or extend through the second gate spacers 230.In some embodiments, the second gate spacers 230 may not include aninner spacer.

The second gate insulation layer 252 may be interposed between the thirdactive pattern 210 and the second gate electrode 254 and between thefourth active pattern 220 and the second gate electrode 254. The secondgate insulation layer 252 may surround the third active pattern 210 andthe fourth active pattern 220. The second gate insulation layer 252 maybe formed on the upper surface of the field insulation layer 105 and anupper surface of the second fin protrusion 200P.

The second gate insulation layer 252 may extend along inner sidewalls ofthe second gate spacers 230. For example, the second gate insulationlayer 252 may extend along sidewalls and a lower surface of the secondtrench TR2.

The second epitaxial patterns 240 may be formed on opposite sides of thesecond gate electrode 254. The second epitaxial patterns 240 may contactthe third active pattern 210, the fourth active pattern 220, and thesecond gate insulation layer 252. For example, the second epitaxialpatterns 240 may be formed on sidewalls of the third active pattern 210,sidewalls of the fourth active pattern 220, and an outer surface of thesecond gate insulation layer 252.

In some embodiments, each of the second epitaxial patterns 240 mayinclude multiple layers. For example, each of the second epitaxialpatterns 240 may include a third epitaxial layer 242 and a fourthepitaxial layer 244 that are sequentially formed on the substrate 100.

In some embodiments, the transistors on the first region I and thesecond region II may be PMOS transistors. For example, each of the firstepitaxial patterns 140 and the second epitaxial patterns 240 may includea p-type impurity.

In some embodiments, the first epitaxial patterns 140 and the secondepitaxial patterns 240 may include a semiconductor material at differentconcentrations. For example, the first epitaxial patterns 140 and thesecond epitaxial patterns 240 may include silicon germanium (SiGe). Insome embodiment, a germanium concentration in each of the firstepitaxial patterns 140 may be higher than that in each of the secondepitaxial patterns 240. In some embodiments, the germanium concentrationin the first epitaxial layer 142 may be higher than that in the thirdepitaxial layer 242.

When the semiconductor device is a PMOS transistor, the source/drainregion including germanium at a high concentration may be damaged duringthe removal process of the sacrificial layers (see, e.g., 2001 of FIG.16). In semiconductor devices according to example embodiments, thefirst epitaxial patterns 140 may be prevented from being damaged byusing the first gate spacers 130 including the semiconductor materiallayer similar to the channel region (e.g., the first and second activepatterns 110 and 120).

FIG. 11 is a perspective view of a semiconductor device according toexample embodiments. FIG. 12 is a cross-sectional view taken along linesE-E′ and F-F′ of FIG. 11. In FIGS. 11 and 12, the same numerals are usedto denote the same elements as shown in FIGS. 1 to 4, 9, and 10.

Referring to FIGS. 11 and 12, in a semiconductor device according toexample embodiments, each of the second gate spacers 230 may include asecond outer spacer 232 and a second inner spacer 234.

The second inner spacer 234 may be formed on a sidewall of the secondgate electrode 254 surrounding the third active pattern 210 and thefourth active pattern 220. The second outer spacer 232 may be formed onthe second inner spacer 234. The second outer spacer 232 may be formedon the fourth active pattern 220.

The second inner spacer 234 nay be formed between the second finprotrusion 200P and the third active pattern 210 and between the thirdactive pattern 210 and the fourth active pattern 220.

In some embodiments, the transistors on the first region I and thesecond region II may be NMOS transistors. For example, each of the firstepitaxial patterns 140 and the second epitaxial patterns 240 may includean n-type impurity.

In some embodiments, the first inner spacer 134 may include asemiconductor material layer similar to the first active pattern 110 andthe second active pattern 120. The second inner spacer 234 may includean insulating material layer.

For example, when the first active pattern 110 and the second activepattern 120 include silicon (Si), the first inner spacer 134 may includesilicon (Si) or silicon germanium (SiGe). For example, when the firstactive pattern 110 and the second active pattern 120 include silicongermanium (SiGe), germanium (Ge), the first inner spacer 134 may includesilicon germanium (SiGe), germanium (Ge).

The second inner spacer 234 may include, e.g., a low-k dielectricmaterial, silicon nitride, silicon oxynitride, silicon oxide, siliconoxycarbonitride, or combinations thereof. The low-k dielectric materialmay have a lower dielectric constant than that of silicon oxide.

In semiconductor devices according to example embodiments, for example,stacking faults in the source/drain region of the transistor that is on,e.g., the first region I may be reduced or prevented, and the parasiticcapacitance between the gate electrode and the source/drain region ofthe transistor that is on, e.g., the second region II may be reduced orprevented.

FIG. 13 is a perspective view of a semiconductor device according toexample embodiments. FIGS. 14 and 15 are cross-sectional views takenalong lines G-G′ and H-H′ of FIG. 13. In FIGS. 13 to 15, the samenumerals are used to denote the same elements as shown in FIGS. 1 to 4,and 9 to 12.

Referring to FIGS. 13 and 14, in a semiconductor device according toexample embodiments, a transistor on the first region I is a PMOStransistor, and a transistor on the second region II is an NMOStransistor. For example, the first epitaxial patterns 140 may include ap-type impurity. The second epitaxial patterns 240 may include an n-typeimpurity.

In some embodiments, the first inner spacer 134 may include a firstsemiconductor material layer similar to the first active pattern 110 andthe second active pattern 120, and the second inner spacer 234 mayinclude a second semiconductor material layer similar to the thirdactive pattern 210 and the fourth active pattern 220.

For example, when the first active pattern 110 and the second activepattern 120 include silicon (Si), the first inner spacer 134 may includesilicon (Si) or silicon germanium (SiGe). For example, when the firstactive pattern 110 and the second active pattern 120 include silicongermanium (SiGe) or germanium (Ge), the first inner spacer 134 mayinclude silicon germanium (SiGe) or germanium (Ge).

For example, when the third active pattern 210 and the fourth activepattern 220 include silicon (Si), the second inner spacer 234 mayinclude silicon (Si) or silicon germanium (SiGe). For example, when thethird active pattern 210 and the fourth active pattern 220 includesilicon germanium (SiGe) or germanium (Ge), the second inner spacer 234may include silicon germanium (SiGe) or germanium (Ge),

Referring to FIGS. 13 and 15, in a semiconductor device according toexample embodiments, a transistor on the first region I is a PMOStransistor, and a transistor on the second transistor II is an NMOStransistor. For example, the first epitaxial patterns 140 may include ap-type impurity. The second epitaxial patterns 240 may include an n-typeimpurity.

In some embodiments, the first inner spacer 134 may include a firstsemiconductor material layer similar to the first active pattern 110 andthe second active pattern 120, and the second inner spacer 234 mayinclude an insulating material layer.

For example, when the first active pattern 110 and the second activepattern 120 include silicon (Si), the first inner spacer 134 may includesilicon (Si) or silicon germanium (SiGe). For example, when the firstactive pattern 110 and the second active pattern 120 include silicongermanium (SiGe) or germanium (Ge), the first inner spacer 134 mayinclude silicon germanium (SiGe) or germanium (Ge).

For example, the second inner spacer 234 may include, e.g., a low-kdielectric material, silicon nitride, silicon oxynitride, silicon oxide,silicon oxycarbonitride, or combinations thereof. The low-k dielectricmaterial may have a lower dielectric constant than that of siliconoxide.

FIGS. 16 to 29 are views illustrating example stages or operations in amethod of manufacturing an image sensor according to exampleembodiments. FIGS. 17, 19, 21, and 23 to 28 are cross-sectional viewstaken along line A-A′ of FIG. 16. FIGS. 18, 20, 22, and 29 arecross-sectional views taken along line B-B′ of FIG. 16. In FIGS. 16 to29, the same numerals are used to denote the same elements as shown inFIGS. 1 to 15.

Referring to FIGS. 16 to 18, a semiconductor stack layer 2000 includingthe sacrificial layers 2001 and the active layers 2002 that arealternately stacked is formed on the substrate 100. The active layers2002 may include a material having an etch selectivity with respect tothe sacrificial layers 2001. The sacrificial layers 2001 and the activelayers 2002 may be formed by an epitaxial growth process.

Referring to FIGS. 16 and 18, two sacrificial layers 2001 and two activelayers 2002 are formed on the substrate 100. However, the number of thesacrificial layers 2001 and the number of the active layers 2002 are notlimited thereto. In addition, the stacked order of the sacrificiallayers 2001 and the active layers 2002 may be varied. For example, inthe semiconductor stack layer 2000, one of the active layers 2002 may bedisposed at an uppermost level, as shown in the drawings. In someembodiments, one of the sacrificial layers 2001 may be disposed at theuppermost level in the semiconductor stack layer 2000.

A first mask pattern 2101 may be formed on the semiconductor stack layer2000. The first mask pattern 2101 may extend lengthwise in the firstdirection X1.

Referring to FIGS. 19 and 20, the semiconductor stack layer 2000 and thesubstrate 100 are etched using the first mask pattern 2101 as an etchmask. Thus, a fin structure F1 may be formed on the substrate 100.

The sacrificial layers 2001 may be etched to form a first sacrificialpattern 112 and a second sacrificial pattern 122 that extend lengthwisein the first direction X1. The active layers 2002 may be etched to formthe first active pattern 110 and a second active pattern 120 that extendlengthwise in the first direction X1.

The fin structure F1 includes the first fin protrusion 100P, the firstsacrificial pattern 112, the first active pattern 110, the secondsacrificial pattern 122, and the second active pattern 120 that aresequentially stacked.

Referring to FIGS. 21 and 22, the field insulation layer 105 is formedon the substrate 100 and cover at least a portion of a sidewall of thefin structure F1. During the process of forming the field insulationlayer 105, the first mask pattern 2101 may be removed.

A dummy gate electrode 150D is formed on the fin structure F1. The dummygate electrode 150D may intersect the fin structure F1 and extendlengthwise in the second direction Y1. The dummy gate electrode 150D maybe formed using a second mask pattern 2102 as an etch mask. Even thoughnot shown in the drawing, a dummy gate insulation layer or a finstructure protection layer may be further formed between the dummy gateelectrode 150D and the fin structure F1.

Preliminary gate spacers 130P are formed on sidewalls of the dummy gateelectrode 150D.

Referring to FIG. 23, the fin structure F1 is etched using the dummygate electrode 150D and the preliminary gate spacers 130P as an etchmask.

Thus, a portion of the first sacrificial pattern 112, a portion of thefirst active pattern 110, a portion of the second sacrificial pattern122, and a portion of the second active pattern 120 may be removed. Insome embodiments, an undercut region may be formed in the fin structureF1. For example, the undercut region may be formed under the dummy gateelectrode 150D and the preliminary gate spacers 130P.

In some embodiments, when the fin structure F1 is etched, the uppersurface of the first fin protrusion 100P may be exposed. In someembodiments, when the fin structure F1 is etched, a portion of the firstfin protrusion 100P may be etched.

Referring to FIG. 24, sidewalls of the first sacrificial pattern 112 andsidewalls of the second sacrificial pattern 122 are selectivelyrecessed.

For example, when the fin structure F1 is etched, the sidewalls of thefirst sacrificial pattern 112 and sidewalls of the first active pattern110, the sidewalls of the second sacrificial pattern 122, and sidewallsof the second active pattern 120 may be exposed. At this time, theexposed sidewalls of the first sacrificial pattern 112 and the exposedsidewalls of the second sacrificial pattern 122 are selectivelyrecessed.

Since the first active pattern 110 and the second active pattern 120include the material having the etch selectivity with respect to thefirst sacrificial pattern 112 and the second sacrificial pattern 122,the first sacrificial pattern 112 and the second sacrificial pattern 122may be selectively etched.

Thus, a first recess RC1 is formed on the sidewalls of the firstsacrificial pattern 112, between the first fin protrusion 100P and thefirst active pattern 110. Additionally, a second recess RC2 is formed onthe sidewalls of the second sacrificial pattern 122, between the firstactive pattern 110 and the second active pattern 120. The sidewalls ofthe first sacrificial pattern 112 and the sidewalls of the secondsacrificial pattern 122 on which the first recess RC1 and the secondrecess RC2 are formed may be flat or planar as shown in the drawing, butare not limited thereto. For example, the sidewalls of the firstsacrificial pattern 112 and the sidewalls of the second sacrificialpattern 122 may have a concave or other curved shape depending on therecess process.

Referring to FIG. 25, an inner spacer layer 134L including a materialsimilar to the first active pattern 110 and the second active pattern120 is formed on the substrate 100. For example, the inner spacer layer134L including a semiconductor material may be formed on the substrate100.

For example, when the first active pattern 110 and the second activepattern 120 include silicon (Si), the inner spacer layer 134L mayinclude silicon (Si) or silicon germanium (SiGe). In this case, asilicon concentration in the inner spacer layer 134L may be higher thanthat in each of the first active pattern 110 and the second activepattern 120. In some embodiments, a silicon concentration in the innerspacer layer 134L may be higher than that in each of the firstsacrificial pattern 112 and the second sacrificial pattern 122

For example, when the first active pattern 110 and the second activepattern 120 are silicon germanium (SiGe) or germanium (Ge), the innerspacer layer 134L may include silicon germanium (SiGe) or germanium(Ge). In this case, a germanium concentration in the inner spacer layer134L may be higher than that in each of the first active pattern 110 andthe second active pattern 120. In some embodiments, a germaniumconcentration in the inner spacer layer 134L may be higher than that ineach of the first sacrificial pattern 112 and the second sacrificialpattern 122.

The inner spacer layer 134L may extend along the upper surface of thefirst fin protrusion 100P, the sidewalls of the first sacrificialpattern 112, the sidewalls of the first active pattern 110, thesidewalls of the second sacrificial pattern 122, and the sidewalls ofthe second active pattern 120. For example, the inner spacer layer 134Lmay extend along profiles of the first fin protrusion 100P, the firstsacrificial pattern 112, the first active pattern 110, the secondsacrificial pattern 122, and the second active pattern 120.

The inner spacer layer 134L may be formed by, e.g., an epitaxial growthprocess, but is not limited thereto. For example, the inner spacer layer134L may be formed by a deposition process. The inner spacer layer 134Lmay be formed of a single layer, but is not limited thereto. In someembodiments, the inner spacer layer 134L may be formed of multiplelayers that include a semiconductor material at differentconcentrations. In some embodiments, the inner spacer layer 134L mayinclude a multiple layered structure in which at least one insulationmaterial layer and at least one semiconductor material layer aresequentially stacked.

Referring to FIG. 26, a portion of the inner spacer layer 134L on thesidewalls of the first and second active patterns 110 and 120 isremoved. Thus, the first gate spacers 130, each of which includes thefirst outer spacer 132 and the first inner spacer 134, are formed.

The removal process of the portion of the inner spacer layer 134L on thesidewalls of the first and second active patterns 110 and 120 may beperformed by an etching process using the dummy gate electrode 150D andthe preliminary gate spacers 130P as an etch mask. The above etchingprocess may include, e.g., a gas phase reaction etching process, aplasma etching process, and/or a wet etching process. In addition, bythe above etching process, a portion of the inner spacer layer 134L onthe upper surface of the first fin protrusion 100P may be removed.

Opposite sidewalls of the first inner spacer 134 may be flat or planar,but are not limited thereto. For example, when the sidewalls of thefirst sacrificial pattern 112 including the first recess RC1 have theconcave curved shape, the sidewall of the first inner spacer 134adjacent to the first sacrificial pattern 112 may have a convex curvedshape. In addition, when the sidewalls of the second sacrificial pattern122 including the second recess RC2 have the concave curved shape, thesidewall of the first inner spacer 134 adjacent to the secondsacrificial pattern 122 may have a convex curved shape.

Referring to FIG. 27, the first epitaxial patterns 140 are formed onopposite sides of the dummy gate electrode 150D.

For example, each of the first epitaxial patterns 140 may be formed bybeing grown from the first fin protrusion 100P, the first active pattern110, the second active pattern 120, and the first inner spacer 134 usingan epitaxial growth process. Thus, each of the first epitaxial patterns140 may contact the first active pattern 110, the second active pattern120, and the first inner spacer 134.

In some embodiments, each of the first epitaxial patterns 140 mayinclude multiple layers. For example, each of the first epitaxialpatterns 140 may include the first epitaxial layer 142 and the secondepitaxial layer 144.

The interlayer insulation layer 160 is formed on the substrate 100 tocover the first epitaxial patterns 140. The dummy gate electrode 150Dmay be exposed by the interlayer insulation layer 160.

For example, the interlayer insulation layer 160 may be formed to coverthe first epitaxial patterns 140 and then may be planarized until anupper surface of the dummy gate electrode 150D is exposed.

The second mask pattern 2102 may be removed during the formation of theinterlayer insulation layer 160.

Referring to FIGS. 28 and 29, the dummy gate electrode 150D, the firstsacrificial pattern 112, and the second sacrificial pattern 122 areremoved. Thus, the first trench TR1 extending lengthwise in the seconddirection Y1 may be formed. The first active pattern 110 and the secondactive pattern 120 may also be exposed.

The first active pattern 110 may be spaced apart from the first finprotrusion 100P. The second active pattern 120 may be spaced apart fromthe first active pattern 110.

Referring again to FIGS. 1 to 4, the first gate insulation layer 152 andthe first gate electrode 154 are formed in the first trench TR1.

The first gate electrode 154 may be formed of a single layer, but is notlimited to thereto. In some embodiments, the first gate electrode 154may be formed of multiple layers. For example, the first gate electrode154 may include a work function control conductive layer and a fillingconductive layer in a space formed by the work function controlconductive layer.

While the present inventive concepts have been shown and described withreference to example embodiments thereof, it will be understood by thoseof ordinary skill in the art that various changes in form and detailsmay be made thereto without departing from the spirit and scope of thepresent inventive concepts as set forth by the following claims.

1. A semiconductor device comprising: a substrate; a gate electrode onthe substrate, the gate electrode extending in a first direction; a gatespacer on a sidewall of the gate electrode, the gate spacer comprising asemiconductor material layer; an active pattern penetrating the gateelectrode and the gate spacer, the active pattern extending in a seconddirection crossing the first direction; and an epitaxial patterncontacting the active pattern and the gate spacer.
 2. The semiconductordevice according to claim 1, wherein the active pattern and thesemiconductor material layer of the gate spacer comprise silicon.
 3. Thesemiconductor device according to claim 2, wherein a siliconconcentration in the semiconductor material layer of the gate spacer ishigher than a silicon concentration in the active pattern.
 4. Thesemiconductor device according to claim 1, wherein the active patternand the semiconductor material layer of the gate spacer comprisegermanium.
 5. The semiconductor device according to claim 4, wherein agermanium concentration in the semiconductor material layer of the gatespacer is higher than a germanium concentration in the active pattern.6. The semiconductor device according to claim 1, wherein the epitaxialpattern contacts the semiconductor material layer of the gate spacer,and wherein the gate spacer is free of an oxide or a nitride.
 7. Thesemiconductor device according to claim 1, wherein the epitaxial patterncomprises a p-type impurity and silicon germanium.
 8. The semiconductordevice according to claim 7, wherein the epitaxial pattern comprises afirst epitaxial pattern and a second epitaxial pattern on the firstepitaxial pattern, the first epitaxial pattern contacts the activepattern and the gate spacer, and a germanium concentration in the secondepitaxial pattern is higher than a germanium concentration in the firstepitaxial pattern.
 9. The semiconductor device according to claim 1,wherein the epitaxial pattern comprises a first impurity, and thesemiconductor material layer of the gate spacer comprises a secondimpurity of a same conductive type as the first impurity.
 10. Thesemiconductor device according to claim 1, wherein the epitaxial patterncomprises a first impurity, and the semiconductor material layer of thegate spacer comprises a second impurity of a different conductive typefrom the first impurity.
 11. A semiconductor device comprising: asubstrate; a first active pattern on the substrate; a gate electrodesurrounding the first active pattern; an inner spacer on a sidewall ofthe gate electrode, wherein the inner spacer is between the first activepattern and the substrate; and an epitaxial pattern contacting the firstactive pattern and the inner spacer, wherein the inner spacer comprisesa semiconductor material.
 12. The semiconductor device according toclaim 11, wherein a sidewall of the inner spacer, which is adjacent tothe gate electrode, has a convex curved shape.
 13. The semiconductordevice according to claim 11, further comprising: an outer spacer on thesidewall of the gate electrode, wherein the outer spacer is disposed onthe first active pattern and the inner spacer.
 14. The semiconductordevice according to claim 13, wherein the outer spacer comprises aninsulating material, and wherein the inner spacer is free of an oxide ora nitride.
 15. The semiconductor device according to claim 11, furthercomprising: a second active pattern on the first active pattern, whereinthe gate electrode further surrounds the second active pattern, andwherein the first and second active patterns extend through the innerspacer to contact the epitaxial pattern.
 16. A semiconductor devicecomprising: a substrate comprising a first region and a second region; afirst gate electrode on the first region, the first gate electrodeextending in a first direction; a first gate spacer on a sidewall of thefirst gate electrode, the first gate spacer comprising a firstsemiconductor material; a first active pattern penetrating the firstgate electrode and the first gate spacer, the first active patternextending in a second direction crossing the first direction; a firstepitaxial pattern on a sidewall of the first gate spacer; a second gateelectrode on the second region, the second gate electrode extending in athird direction; a second active pattern penetrating the second gateelectrode, the second active pattern extending in a fourth directioncrossing the third direction; and a second epitaxial pattern on asidewall of the second gate electrode.
 17. The semiconductor deviceaccording to claim 16, further comprising: a gate insulation layerbetween the second gate electrode and the second epitaxial pattern, thegate insulation layer contacting the second epitaxial pattern, whereinthe first epitaxial pattern and the second epitaxial pattern comprise ap-type impurity.
 18. The semiconductor device according to claim 16,further comprising: a second gate spacer between the second epitaxialpattern and the second gate electrode, the second gate spacer contactingthe second epitaxial pattern, wherein the first epitaxial pattern andthe second epitaxial pattern comprise an n-type impurity, and the secondgate spacer comprises an insulating material.
 19. The semiconductordevice according to claim 16, further comprising: a second gate spacerbetween the second epitaxial pattern and the second gate electrode, thesecond gate spacer contacting the second epitaxial pattern, wherein thefirst epitaxial pattern comprises a p-type impurity, the secondepitaxial pattern comprises an n-type impurity, and the second gatespacer comprises an insulating material.
 20. The semiconductor deviceaccording to claim 16, further comprising: a second gate spacer betweenthe second epitaxial pattern and the second gate electrode, the secondgate spacer contacting the second epitaxial pattern, wherein the firstepitaxial pattern comprises a p-type impurity, the second epitaxialpattern comprises an n-type impurity, and the second gate spacercomprises a second semiconductor material. 21.-25. (canceled)